srctree

const impl = if (builtin.cpu.arch == .x86_64 and builtin.zig_backend != .stage2_c and builtin.zig_backend != .stage2_x86_64 and has_aesni and has_avx) impl: {

const compress = if (builtin.cpu.arch == .x86_64 and builtin.zig_backend != .stage2_x86_64)

const SalsaImpl = if (builtin.cpu.arch == .x86_64 and builtin.zig_backend != .stage2_x86_64) SalsaVecImpl else SalsaNonVecImpl;

.x86_64 => if (builtin.zig_backend != .stage2_c and builtin.zig_backend != .stage2_x86_64 and comptime std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sha, .avx2 })) {

try testing.expect(hasUniqueRepresentation(@Vector(4, u16)));

const chunk_len = std.simd.suggestVectorLength(u8) orelse 1;

const Chunk = @Vector(chunk_len, u8);

// Fast path. Check for and skip ASCII characters at the start of the input.

while (remaining.len >= chunk_len) {

const chunk: Chunk = remaining[0..chunk_len].*;

const mask: Chunk = @splat(0x80);

if (@reduce(.Or, chunk & mask == mask)) {

// found a non ASCII byte

break;

remaining = remaining[chunk_len..];

try testing.expect(std.mem.eql(u8, "a", it1.nextCodepointSlice().?));

try testing.expect(std.mem.eql(u8, "b", it1.nextCodepointSlice().?));

try testing.expect(std.mem.eql(u8, "c", it1.nextCodepointSlice().?));

try testing.expect(std.mem.eql(u8, "東", it1.nextCodepointSlice().?));

try testing.expect(std.mem.eql(u8, "京", it1.nextCodepointSlice().?));

try testing.expect(std.mem.eql(u8, "市", it1.nextCodepointSlice().?));

try testing.expect(std.mem.eql(u8, "n", it.nextCodepointSlice().?));

try testing.expect(std.mem.eql(u8, "o", it.peek(1)));

try testing.expect(std.mem.eql(u8, "oë", it.peek(2)));

try testing.expect(std.mem.eql(u8, "oël", it.peek(3)));

try testing.expect(std.mem.eql(u8, "oël", it.peek(4)));

try testing.expect(std.mem.eql(u8, "oël", it.peek(10)));

try testing.expect(std.mem.eql(u8, "o", it.nextCodepointSlice().?));

try testing.expect(std.mem.eql(u8, "ë", it.nextCodepointSlice().?));

try testing.expect(std.mem.eql(u8, "l", it.nextCodepointSlice().?));

try testing.expect(std.mem.eql(u8, &[_]u8{}, it.peek(1)));

array_list: *std.ArrayList(u8),

// optimistically guess that it will all be ascii.

try array_list.ensureTotalCapacityPrecise(utf16le.len);

if (builtin.zig_backend != .stage2_x86_64) {

const chunk_len = std.simd.suggestVectorLength(u16) orelse 1;

const mask: Chunk = @splat(std.mem.nativeToLittle(u16, 0x7F));

const chunk_byte_len = chunk_len * 2;

const chunk_bytes: @Vector(chunk_byte_len, u8) = (std.mem.sliceAsBytes(remaining)[0..chunk_byte_len]).*;

const deinterlaced_bytes = std.simd.deinterlace(2, chunk_bytes);

const ascii_bytes: [chunk_len]u8 = deinterlaced_bytes[0];

array_list.appendSliceAssumeCapacity(&ascii_bytes);

var out_index: usize = array_list.items.len;

try array_list.resize(array_list.items.len + utf8_len);

assert((utf8Encode(codepoint, array_list.items[out_index..]) catch unreachable) == utf8_len);

out_index += utf8_len;

try array_list.resize(array_list.items.len + utf8_len);

assert((wtf8Encode(codepoint, array_list.items[out_index..]) catch unreachable) == utf8_len);

out_index += utf8_len;

pub fn utf16LeToUtf8ArrayList(array_list: *std.ArrayList(u8), utf16le: []const u16) Utf16LeToUtf8AllocError!void {

return utf16LeToUtf8ArrayListImpl(array_list, utf16le, .cannot_encode_surrogate_half);

try utf16LeToUtf8ArrayList(&result, utf16le);

 

try utf16LeToUtf8ArrayList(&result, utf16le);

 

var end_index: usize = 0;

if (builtin.zig_backend != .stage2_x86_64) {

const chunk_len = std.simd.suggestVectorLength(u16) orelse 1;

const mask: Chunk = @splat(std.mem.nativeToLittle(u16, 0x7F));

const chunk_byte_len = chunk_len * 2;

const chunk_bytes: @Vector(chunk_byte_len, u8) = (std.mem.sliceAsBytes(remaining)[0..chunk_byte_len]).*;

const deinterlaced_bytes = std.simd.deinterlace(2, chunk_bytes);

const ascii_bytes: [chunk_len]u8 = deinterlaced_bytes[0];

@memcpy(utf8[end_index .. end_index + chunk_len], &ascii_bytes);

end_index += chunk_len;

end_index += utf8Encode(codepoint, utf8[end_index..]) catch |err| switch (err) {

end_index += wtf8Encode(codepoint, utf8[end_index..]) catch |err| switch (err) {

return end_index;

fn utf8ToUtf16LeArrayListImpl(array_list: *std.ArrayList(u16), utf8: []const u8, comptime surrogates: Surrogates) !void {

// optimistically guess that it will not require surrogate pairs

try array_list.ensureTotalCapacityPrecise(utf8.len);

// Need support for std.simd.interlace

if (builtin.zig_backend != .stage2_x86_64 and comptime !builtin.cpu.arch.isMIPS()) {

const chunk_len = std.simd.suggestVectorLength(u8) orelse 1;

const zeroes: Chunk = @splat(0);

const utf16_chunk: [chunk_len * 2]u8 align(@alignOf(u16)) = std.simd.interlace(.{ chunk, zeroes });

array_list.appendSliceAssumeCapacity(std.mem.bytesAsSlice(u16, &utf16_chunk));

const short = @as(u16, @intCast(codepoint));

try array_list.append(mem.nativeToLittle(u16, short));

var out: [2]u16 = undefined;

out[0] = mem.nativeToLittle(u16, high);

out[1] = mem.nativeToLittle(u16, low);

try array_list.appendSlice(out[0..]);

pub fn utf8ToUtf16LeArrayList(array_list: *std.ArrayList(u16), utf8: []const u8) error{ InvalidUtf8, OutOfMemory }!void {

return utf8ToUtf16LeArrayListImpl(array_list, utf8, .cannot_encode_surrogate_half);

 

 

var dest_i: usize = 0;

// Need support for std.simd.interlace

if (builtin.zig_backend != .stage2_x86_64 and comptime !builtin.cpu.arch.isMIPS()) {

const chunk_len = std.simd.suggestVectorLength(u8) orelse 1;

const zeroes: Chunk = @splat(0);

const utf16_bytes: [chunk_len * 2]u8 align(@alignOf(u16)) = std.simd.interlace(.{ chunk, zeroes });

@memcpy(utf16le[dest_i..][0..chunk_len], std.mem.bytesAsSlice(u16, &utf16_bytes));

dest_i += chunk_len;

var src_i: usize = 0;

while (src_i < remaining.len) {

const n = utf8ByteSequenceLength(remaining[src_i]) catch return switch (surrogates) {

.cannot_encode_surrogate_half => error.InvalidUtf8,

.can_encode_surrogate_half => error.InvalidWtf8,

};

const next_src_i = src_i + n;

const codepoint = switch (surrogates) {

.cannot_encode_surrogate_half => utf8Decode(remaining[src_i..next_src_i]) catch return error.InvalidUtf8,

.can_encode_surrogate_half => wtf8Decode(remaining[src_i..next_src_i]) catch return error.InvalidWtf8,

};

const short = @as(u16, @intCast(codepoint));

utf16le[dest_i] = mem.nativeToLittle(u16, short);

dest_i += 1;

utf16le[dest_i] = mem.nativeToLittle(u16, high);

utf16le[dest_i + 1] = mem.nativeToLittle(u16, low);

dest_i += 2;

src_i = next_src_i;

return dest_i;

var utf16le: [2]u16 = [_]u16{0} ** 2;

try testing.expectEqual(@as(usize, 2), length);

try testing.expectEqualSlices(u8, "\x01\xd8\x37\xdc", mem.sliceAsBytes(utf16le[0..]));

try testing.expectEqual(@as(usize, 2), length);

try testing.expectEqualSlices(u8, "\xff\xdb\xff\xdf", mem.sliceAsBytes(utf16le[0..]));

try testing.expectEqualSlices(u8, "\x01\xd8\x37\xdc", mem.sliceAsBytes(utf16[0..]));

try testing.expectEqualSlices(u8, "\xff\xdb\xff\xdf", mem.sliceAsBytes(utf16[0..]));

pub fn utf8ToUtf16LeStringLiteral(comptime utf8: []const u8) *const [calcUtf16LeLen(utf8) catch unreachable:0]u16 {

const len: usize = calcUtf16LeLen(utf8) catch |err| @compileError(err);

try expectFmt("퟿", "{}", .{fmtUtf16Le(&[_]u16{std.mem.readInt(u16, "\xff\xd7", native_endian)})});

try expectFmt("�", "{}", .{fmtUtf16Le(&[_]u16{std.mem.readInt(u16, "\x00\xd8", native_endian)})});

try expectFmt("�", "{}", .{fmtUtf16Le(&[_]u16{std.mem.readInt(u16, "\xff\xdb", native_endian)})});

try expectFmt("�", "{}", .{fmtUtf16Le(&[_]u16{std.mem.readInt(u16, "\x00\xdc", native_endian)})});

try expectFmt("�", "{}", .{fmtUtf16Le(&[_]u16{std.mem.readInt(u16, "\xff\xdf", native_endian)})});

try expectFmt("", "{}", .{fmtUtf16Le(&[_]u16{std.mem.readInt(u16, "\x00\xe0", native_endian)})});

pub fn wtf16LeToWtf8ArrayList(array_list: *std.ArrayList(u8), utf16le: []const u16) mem.Allocator.Error!void {

return utf16LeToUtf8ArrayListImpl(array_list, utf16le, .can_encode_surrogate_half);

try wtf16LeToWtf8ArrayList(&result, wtf16le);

 

try wtf16LeToWtf8ArrayList(&result, wtf16le);

 

pub fn wtf8ToWtf16LeArrayList(array_list: *std.ArrayList(u16), wtf8: []const u8) error{ InvalidWtf8, OutOfMemory }!void {

return utf8ToUtf16LeArrayListImpl(array_list, wtf8, .can_encode_surrogate_half);

 

 

.bytes = std.mem.sliceAsBytes(s),

code_units[0] = std.mem.readInt(u16, it.bytes[it.i..][0..2], .little);

code_units[1] = std.mem.readInt(u16, it.bytes[it.i..][0..2], .little);

std.mem.nativeToLittle(u16, 0xD83D), // high surrogate

std.mem.nativeToLittle(u16, 0xDCA9), // low surrogate

std.mem.nativeToLittle(u16, 0xD83D), // high surrogate

std.mem.nativeToLittle(u16, ' '), // not surrogate

std.mem.nativeToLittle(u16, 0xDCA9), // low surrogate

std.mem.nativeToLittle(u16, 0xD800), // high surrogate

std.mem.nativeToLittle(u16, 0xDBFF), // high surrogate

std.mem.nativeToLittle(u16, 0xD800), // high surrogate

std.mem.nativeToLittle(u16, 0xE000), // not surrogate

std.mem.nativeToLittle(u16, 0xD7FF), // not surrogate

std.mem.nativeToLittle(u16, 0xDC00), // low surrogate

std.mem.nativeToLittle(u16, 0x61), // not surrogate

std.mem.nativeToLittle(u16, 0xDC00), // low surrogate

std.mem.nativeToLittle(u16, 0xDC00), // low surrogate

/// negative values for `this_index` indicate "don't care" so we arbitrarily choose 0

if (this_index <= 0) return 0;

 

const positive_index = @as(usize, @intCast(this_index));

try testing.expect(shuffleVectorIndex(-1, vector_len) == 0);

.c_longdouble_type,

else => ip.indexToKey(ty) == .int_type,

else => if (ty.isPtrAtRuntime(mod)) return,

/// Should coercion to comptime_int ermit an error message.

if (opts.update_tracking) ({}) else std.heap.stackFallback(@sizeOf(ExpectedContents), self.gpa);

const dst_bits = dst_ty.floatBits(self.target.*);

const src_bits = src_ty.floatBits(self.target.*);

.return_type = self.floatCompilerRtAbiType(dst_ty, src_ty).toIntern(),

.param_types = &.{self.floatCompilerRtAbiType(src_ty, dst_ty).toIntern()},

} }, &.{src_ty}, &.{.{ .air_ref = ty_op.operand }});

const dst_reg = dst_mcv.getReg().?.to128();

try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg, mat_src_reg.to128());

dst_reg,

dst_reg,

dst_reg,

if (self.hasFeature(.avx)) if (src_mcv.isMemory()) try self.asmRegisterRegisterMemory(

.{ .v_sd, .cvtss2 },

dst_reg,

dst_reg,

try src_mcv.mem(self, .dword),

) else try self.asmRegisterRegisterRegister(

.{ .v_sd, .cvtss2 },

dst_reg,

dst_reg,

(if (src_mcv.isRegister())

src_mcv.getReg().?

else

try self.copyToTmpRegister(src_ty, src_mcv)).to128(),

) else if (src_mcv.isMemory()) try self.asmRegisterMemory(

.{ ._sd, .cvtss2 },

dst_reg,

try src_mcv.mem(self, .dword),

.{ ._sd, .cvtss2 },

dst_reg,

(if (src_mcv.isRegister())

try self.copyToTmpRegister(src_ty, src_mcv)).to128(),

};

const result: MCValue = result: {

const src_ty = self.typeOf(ty_op.operand);

 

const dst_ty = self.typeOfIndex(inst);

const abi_size: u32 = @intCast(dst_ty.abiSize(mod));

 

const min_ty = if (dst_int_info.bits < src_int_info.bits) dst_ty else src_ty;

.{ .register = registerAlias(dst_mcv.getReg().?, abi_size) }

break :result .{ .register = registerAlias(dst_mcv.getReg().?, abi_size) };

};

else if (dst_abi_size <= 16) dst: {

const dst_mcv = try self.allocRegOrMem(inst, true);

try self.genCopy(dst_ty, dst_mcv, src_mcv, .{});

const dst_info = dst_ty.childType(mod).intInfo(mod);

const src_info = src_ty.childType(mod).intInfo(mod);

const mir_tag = @as(?Mir.Inst.FixedTag, switch (dst_info.bits) {

8 => switch (src_info.bits) {

16 => switch (dst_ty.vectorLen(mod)) {

16 => switch (src_info.bits) {

32 => switch (dst_ty.vectorLen(mod)) {

const elem_ty = src_ty.childType(mod);

const mask_val = try mod.intValue(elem_ty, @as(u64, math.maxInt(u64)) >> @intCast(64 - dst_info.bits));

.child = elem_ty.ip_index,

const dst_reg = registerAlias(dst_mcv.getReg().?, src_abi_size);

dst_reg,

dst_reg,

try self.asmRegisterRegisterRegister(mir_tag, dst_reg, dst_reg, dst_reg);

dst_reg,

try self.asmRegisterRegister(mir_tag, dst_reg, dst_reg);

const limb_len = std.math.divCeil(u32, abi_size, 8) catch unreachable;

try self.register_manager.getReg(.rcx, null);

try self.register_manager.getReg(.st0, inst);

const limb_len = std.math.divCeil(u31, abi_size, 8) catch unreachable;

Immediate.u(std.math.maxInt(u6)),

Immediate.u(std.math.maxInt(u6)),

Immediate.u(shift_imm & std.math.maxInt(u6)),

Immediate.u(shift_imm & std.math.maxInt(u6)),

try self.register_manager.getReg(.rcx, null);

const limb_len = std.math.divCeil(u32, src_abi_size, 8) catch unreachable;

try self.register_manager.getReg(.rax, track_inst_rax);

try self.register_manager.getReg(.rdx, track_inst_rdx);

try self.register_manager.getReg(.rax, null);

try self.register_manager.getReg(.rdx, if (signedness == .unsigned) maybe_inst else null);

try self.register_manager.getReg(.rax, if (signedness == .unsigned) maybe_inst else null);

try self.register_manager.getReg(.rdx, null);

try self.register_manager.getReg(.xmm0, null);

try self.asmRegisterRegister(

@as(?Mir.Inst.FixedTag, switch (lhs_ty.zigTypeTag(mod)) {

.Float => switch (lhs_ty.floatBits(self.target.*)) {

32 => .{ ._ps, .@"and" },

64 => .{ ._pd, .@"and" },

.Vector => switch (lhs_ty.childType(mod).zigTypeTag(mod)) {

.Float => switch (lhs_ty.childType(mod).floatBits(self.target.*)) {

32 => switch (lhs_ty.vectorLen(mod)) {

1...4 => .{ ._ps, .@"and" },

else => null,

},

64 => switch (lhs_ty.vectorLen(mod)) {

1...2 => .{ ._pd, .@"and" },

else => null,

},

16, 80, 128 => null,

else => unreachable,

},

else => unreachable,

},

}) orelse return self.fail("TODO implement genBinOp for {s} {}", .{

@tagName(air_tag), lhs_ty.fmt(mod),

}),

dst_reg,

mask_reg,

);

try self.asmRegisterRegister(

@as(?Mir.Inst.FixedTag, switch (lhs_ty.zigTypeTag(mod)) {

.Float => switch (lhs_ty.floatBits(self.target.*)) {

32 => .{ ._ps, .andn },

64 => .{ ._pd, .andn },

16, 80, 128 => null,

else => unreachable,

},

.Vector => switch (lhs_ty.childType(mod).zigTypeTag(mod)) {

.Float => switch (lhs_ty.childType(mod).floatBits(self.target.*)) {

32 => switch (lhs_ty.vectorLen(mod)) {

1...4 => .{ ._ps, .andn },

else => null,

},

64 => switch (lhs_ty.vectorLen(mod)) {

1...2 => .{ ._pd, .andn },

else => null,

},

16, 80, 128 => null,

else => unreachable,

},

else => unreachable,

},

else => unreachable,

}) orelse return self.fail("TODO implement genBinOp for {s} {}", .{

@tagName(air_tag), lhs_ty.fmt(mod),

}),

mask_reg,

lhs_copy_reg.?,

);

try self.asmRegisterRegister(

@as(?Mir.Inst.FixedTag, switch (lhs_ty.zigTypeTag(mod)) {

.Float => switch (lhs_ty.floatBits(self.target.*)) {

32 => .{ ._ps, .@"or" },

64 => .{ ._pd, .@"or" },

16, 80, 128 => null,

else => unreachable,

},

.Vector => switch (lhs_ty.childType(mod).zigTypeTag(mod)) {

.Float => switch (lhs_ty.childType(mod).floatBits(self.target.*)) {

32 => switch (lhs_ty.vectorLen(mod)) {

1...4 => .{ ._ps, .@"or" },

else => null,

},

64 => switch (lhs_ty.vectorLen(mod)) {

1...2 => .{ ._pd, .@"or" },

else => null,

},

16, 80, 128 => null,

else => unreachable,

},

else => unreachable,

},

else => unreachable,

}) orelse return self.fail("TODO implement genBinOp for {s} {}", .{

@tagName(air_tag), lhs_ty.fmt(mod),

}),

dst_reg,

mask_reg,

);

const ty = self.typeOf(bin_op.lhs);

try self.spillEflagsIfOccupied();

 

const lhs_mcv = try self.resolveInst(bin_op.lhs);

const lhs_locks: [2]?RegisterLock = switch (lhs_mcv) {

.register => |lhs_reg| .{ self.register_manager.lockRegAssumeUnused(lhs_reg), null },

.register_pair => |lhs_regs| locks: {

const locks = self.register_manager.lockRegsAssumeUnused(2, lhs_regs);

break :locks .{ locks[0], locks[1] };

},

.register_offset => |lhs_ro| .{

self.register_manager.lockRegAssumeUnused(lhs_ro.reg),

null,

},

else => .{null} ** 2,

};

defer for (lhs_locks) |lhs_lock| if (lhs_lock) |lock| self.register_manager.unlockReg(lock);

 

const rhs_mcv = try self.resolveInst(bin_op.rhs);

const rhs_locks: [2]?RegisterLock = switch (rhs_mcv) {

.register => |rhs_reg| .{ self.register_manager.lockReg(rhs_reg), null },

.register_pair => |rhs_regs| self.register_manager.lockRegs(2, rhs_regs),

.register_offset => |rhs_ro| .{ self.register_manager.lockReg(rhs_ro.reg), null },

else => .{null} ** 2,

};

defer for (rhs_locks) |rhs_lock| if (rhs_lock) |lock| self.register_manager.unlockReg(lock);

 

var mnem_size: ?Memory.Size = null;

const mnem_tag = mnem: {

mnem_size = if (mem.endsWith(u8, mnem_str, "b"))

.byte

else if (mem.endsWith(u8, mnem_str, "w"))

.word

else if (mem.endsWith(u8, mnem_str, "l"))

.dword

else if (mem.endsWith(u8, mnem_str, "q"))

.qword

else if (mem.endsWith(u8, mnem_str, "t"))

.tbyte

else

break :mnem null;

break :mnem std.meta.stringToEnum(Instruction.Mnemonic, mnem_str[0 .. mnem_str.len - 1]);

} orelse mnem: {

break :mnem std.meta.stringToEnum(Instruction.Mnemonic, mnem_str);

} orelse return self.fail("invalid mnemonic: '{s}'", .{mnem_str});

8 => switch (ty.vectorLen(mod)) {

1 => if (self.hasFeature(.avx)) return .{ .vex_insert_extract = .{

.insert = .{ .vp_b, .insr },

.extract = .{ .vp_b, .extr },

} } else if (self.hasFeature(.sse4_2)) return .{ .insert_extract = .{

.insert = .{ .p_b, .insr },

.extract = .{ .p_b, .extr },

} },

2 => return if (self.hasFeature(.avx)) .{ .vex_insert_extract = .{

.insert = .{ .vp_w, .insr },

.extract = .{ .vp_w, .extr },

} } else .{ .insert_extract = .{

.insert = .{ .p_w, .insr },

.extract = .{ .p_w, .extr },

} },

3...4 => return .{ .move = if (self.hasFeature(.avx))

.{ .v_d, .mov }

else

.{ ._d, .mov } },

5...8 => return .{ .move = if (self.hasFeature(.avx))

.{ .v_q, .mov }

else

.{ ._q, .mov } },

9...16 => return .{ .move = if (self.hasFeature(.avx))

16 => switch (ty.vectorLen(mod)) {

1 => return if (self.hasFeature(.avx)) .{ .vex_insert_extract = .{

.insert = .{ .vp_w, .insr },

.extract = .{ .vp_w, .extr },

} } else .{ .insert_extract = .{

.insert = .{ .p_w, .insr },

.extract = .{ .p_w, .extr },

} },

2 => return .{ .move = if (self.hasFeature(.avx))

.{ .v_d, .mov }

else

.{ ._d, .mov } },

3...4 => return .{ .move = if (self.hasFeature(.avx))

.{ .v_q, .mov }

else

.{ ._q, .mov } },

5...8 => return .{ .move = if (self.hasFeature(.avx))

32 => switch (ty.vectorLen(mod)) {

1 => return .{ .move = if (self.hasFeature(.avx))

.{ .v_d, .mov }

else

.{ ._d, .mov } },

2 => return .{ .move = if (self.hasFeature(.avx))

.{ .v_q, .mov }

else

.{ ._q, .mov } },

3...4 => return .{ .move = if (self.hasFeature(.avx))

64 => switch (ty.vectorLen(mod)) {

1 => return .{ .move = if (self.hasFeature(.avx))

.{ .v_q, .mov }

else

.{ ._q, .mov } },

2 => return .{ .move = if (self.hasFeature(.avx))

128 => switch (ty.vectorLen(mod)) {

256 => switch (ty.vectorLen(mod)) {

1 => return .{ .move = if (self.hasFeature(.avx))

.{ .v_q, .mov }

else

.{ ._q, .mov } },

2 => return .{ .move = if (self.hasFeature(.avx))

1 => return if (self.hasFeature(.avx)) .{ .vex_insert_extract = .{

.insert = .{ .vp_w, .insr },

.extract = .{ .vp_w, .extr },

} } else .{ .insert_extract = .{

.insert = .{ .p_w, .insr },

.extract = .{ .p_w, .extr },

} },

2 => return .{ .move = if (self.hasFeature(.avx))

.{ .v_d, .mov }

else

.{ ._d, .mov } },

3...4 => return .{ .move = if (self.hasFeature(.avx))

.{ .v_q, .mov }

else

.{ ._q, .mov } },

5...8 => return .{ .move = if (self.hasFeature(.avx))

1 => return .{ .move = if (self.hasFeature(.avx))

.{ .v_ss, .mov }

else

.{ ._ss, .mov } },

2 => return .{ .move = if (self.hasFeature(.avx))

.{ .v_sd, .mov }

else

.{ ._sd, .mov } },

3...4 => return .{ .move = if (self.hasFeature(.avx))

1 => return .{ .move = if (self.hasFeature(.avx))

.{ .v_sd, .mov }

else

.{ ._sd, .mov } },

2 => return .{ .move = if (self.hasFeature(.avx))

std.math.log2_int_ceil(u10, @divExact(dst_reg.bitSize(), 8)),

1...2 => .{ .vp_i128, .broadcast },

if (mir_tag[0] == .vp_i128) break :avx2;

Immediate.u(0),

_ = extra;

return self.fail("TODO implement airSelect for x86_64", .{});

//return self.finishAir(inst, result, .{ pl_op.operand, extra.lhs, extra.rhs });

_ = ty_pl;

return self.fail("TODO implement airShuffle for x86_64", .{});

//return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });

if (result_ty.isVector(mod) and elem_ty.bitSize(mod) == 1) {

.float_combine => try mod.vectorType(.{ .len = 2, .child = .f32_type }),

pabsb, pabsd, pabsw, palignr,

vpalignr, vpand, vpandn, vpclmulqdq,

vpshufd, vpshufhw, vpshuflw,

vpbroadcastb, vpbroadcastd, vpbroadcasti128, vpbroadcastq, vpbroadcastw,

.mrr, .rrm => inst.data.rrx.fixes,

/// VEX-Encoded Packed ___ Integer Data

vp_i128,

/// Uses `rx` payload.

.{ .vpbroadcasti128, .rm, &.{ .ymm, .m128 }, &.{ 0x66, 0x0f, 0x38, 0x5a }, 0, .vex_256_w0, .avx2 },

if (Type.fromInterned(vector_type.child).bitSize(mod) == 1) {

} else switch (aggregate.storage) {

.bytes => |bytes| try code.appendSlice(bytes),

.elems, .repeated_elem => {

var index: u64 = 0;

while (index < vector_type.len) : (index += 1) {

switch (try generateSymbol(bin_file, src_loc, .{

.ty = Type.fromInterned(vector_type.child),

.val = Value.fromInterned(switch (aggregate.storage) {

.bytes => unreachable,

.elems => |elems| elems[

math.cast(usize, index) orelse return error.Overflow

],

.repeated_elem => |elem| elem,

}),

}, code, debug_output, reloc_info)) {

.ok => {},

.fail => |em| return .{ .fail = em },

}

},

}

const padding = abi_size - (math.cast(usize, math.divCeil(

u64,

Type.fromInterned(vector_type.child).bitSize(mod) * vector_type.len,

8,

) catch |err| switch (err) {

error.DivisionByZero => unreachable,

else => |e| return e,

}) orelse return error.Overflow);

if (padding > 0) try code.appendNTimes(0, padding);

try writer.writeByte(' ');

try writer.writeByte(' ');

try writer.writeAll(" = ");

// (A && B) || (C && (A == B))

// A = lhs.is_null ; B = rhs.is_null ; C = rhs.payload == lhs.payload

 

switch (operator) {

.eq => {},

.neq => try writer.writeByte('!'),

else => unreachable,

}

try writer.writeAll("((");

try writer.writeAll(".is_null && ");

try writer.writeAll(".is_null) || (");

try f.writeCValue(writer, lhs, .Other);

try writer.writeAll(".payload == ");

try f.writeCValue(writer, rhs, .Other);

try writer.writeAll(".payload && ");

try f.writeCValue(writer, lhs, .Other);

try writer.writeAll(".is_null == ");

try f.writeCValue(writer, rhs, .Other);

try writer.writeAll(".is_null));\n");

 

return local;

 

try f.writeCValue(writer, lhs, .Other);

try writer.writeByte(' ');

try writer.writeAll(compareOperatorC(operator));

try writer.writeByte(' ');

try f.writeCValue(writer, rhs, .Other);

try writer.writeAll(";\n");

const operation = if (inst_ty.isRuntimeFloat() and operand_ty.isRuntimeFloat())

if (inst_ty.floatBits(target) < operand_ty.floatBits(target)) "trunc" else "extend"

else if (inst_ty.isInt(mod) and operand_ty.isRuntimeFloat())

if (inst_ty.isSignedInt(mod)) "fix" else "fixuns"

else if (inst_ty.isRuntimeFloat() and operand_ty.isInt(mod))

if (operand_ty.isSignedInt(mod)) "float" else "floatun"

 

try writer.writeAll(" = ");

if (inst_ty.isInt(mod) and operand_ty.isRuntimeFloat()) {

try f.object.dg.renderTypeForBuiltinFnName(writer, inst_ty);

try writer.writeAll(compilerRtAbbrev(operand_ty, mod));

try writer.writeAll(compilerRtAbbrev(inst_ty, mod));

if (inst_ty.isInt(mod) and operand_ty.isRuntimeFloat()) {

try f.object.dg.renderBuiltinInfo(writer, inst_ty, .bits);

try writer.writeAll(";\n");

if (!ref_ret) try writer.print(" {s} {}", .{

.lt => "<",

.lte => "<=",

.eq => "==",

.gte => ">=",

.gt => ">",

.neq => "!=",

const dest_bits = dest_ty.floatBits(target);

const src_bits = operand_ty.floatBits(target);

const bits_u64 = try bitSizeAdvanced(Type.fromInterned(vector_type.child), mod, opt_sema);

const bits: u32 = @intCast(bits_u64);

const bytes = ((bits * vector_type.len) + 7) / 8;

const alignment = std.math.ceilPowerOfTwoAssert(u32, bytes);

return .{ .scalar = Alignment.fromByteUnits(alignment) };

const elem_bits = try Type.fromInterned(vector_type.child).bitSizeAdvanced(mod, opt_sema);

const total_bits = elem_bits * vector_type.len;

const total_bytes = (total_bits + 7) / 8;

return self.isSignedInt(mod) or self.isUnsignedInt(mod);

if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf and builtin.target.ofmt != .macho) return error.SkipZigTest;

if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO

const up1 = @as(@Vector(2, u16), up0);

const up2 = @as(@Vector(2, u32), up0);

const up3 = @as(@Vector(2, u64), up0);

const down1 = @as(@Vector(2, u32), @intCast(down0));

const down2 = @as(@Vector(2, u16), @intCast(down0));

const down3 = @as(@Vector(2, u8), @intCast(down0));

 

fn doTheTestFloat() !void {

var vec: @Vector(2, f32) = @splat(1234.0);

_ = &vec;

const wider: @Vector(2, f64) = vec;

try expect(wider[0] == 1234.0);

try expect(wider[1] == 1234.0);

}

try S.doTheTestFloat();

try comptime S.doTheTestFloat();

var a: @Vector(3, f64) = .{ 1.5, 2.5, 3.5 };

_ = &a;

const b: @Vector(3, f32) = @floatCast(a);

try expectEqual(@Vector(3, f32){ 1.5, 2.5, 3.5 }, b);

test "equality compare optional with non-optional" {

try test_cmp_optional_non_optional();

try comptime test_cmp_optional_non_optional();

fn test_cmp_optional_non_optional() !void {

var ten: i32 = 10;

var opt_ten: ?i32 = 10;

var five: i32 = 5;

var int_n: ?i32 = null;

_ = .{ &ten, &opt_ten, &five, &int_n };

try expect(int_n != ten);

try expect(opt_ten == ten);

try expect(opt_ten != five);

// test evaluation is always lexical

// ensure that the optional isn't always computed before the non-optional

var mutable_state: i32 = 0;

_ = blk1: {

mutable_state += 1;

break :blk1 @as(?f64, 10.0);

} != blk2: {

try expect(mutable_state == 1);

break :blk2 @as(f64, 5.0);

};

_ = blk1: {

mutable_state += 1;

break :blk1 @as(f64, 10.0);

} != blk2: {

try expect(mutable_state == 2);

break :blk2 @as(?f64, 5.0);

};

if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO

if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO

if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO

!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest; // TODO

if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO

var v4_a = __v4hi{ 0, 0, 0, 0 };

var v4_b = __v4hi{ 0, 0, 0, 0 };

std.zig.c_translation.shuffleVectorIndex(0, @typeInfo(@TypeOf(v4_a)).Vector.len),

std.zig.c_translation.shuffleVectorIndex(0, @typeInfo(@TypeOf(v4_a)).Vector.len),

std.zig.c_translation.shuffleVectorIndex(0, @typeInfo(@TypeOf(v4_a)).Vector.len),

_ = shuffled;

try expect(@alignOf(@Vector(2, u8)) == 2);

try expect(@alignOf(@Vector(2, u1)) == 1);

try expect(@alignOf(@Vector(1, u1)) == 1);

try expect(@alignOf(@Vector(2, u16)) == 4);

if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO