srctree

Johan Norberg parent c1f39fb8 82517a9b
Add undocumented op code 0x82 for nop immediate

core/include/nes/core/opcode.h added: 18, removed: 6, total 12
@@ -125,6 +125,7 @@ enum Instruction : uint8_t {
RraAbsoluteX = 0x7F, // Undocumented
NopImmediate80 = 0x80, // Undocumented
StaIndexedIndirect = 0x81,
NopImmediate82 = 0x82, // Undocumented
SaxIndirectX = 0x83, // Undocumented
StyZeropage = 0x84,
StaZeropage = 0x85,
@@ -448,6 +449,8 @@ struct Opcode {
return {Family::ROR, RorAbsoluteX, AddressMode::AbsoluteX};
case NopImmediate80:
return {Family::NOP, NopImmediate80, AddressMode::Immediate};
case NopImmediate82:
return {Family::NOP, NopImmediate82, AddressMode::Immediate};
case StaIndexedIndirect:
return {Family::STA, StaIndexedIndirect, AddressMode::IndexedIndirect};
case StyZeropage:
 
core/src/mos6502.cpp added: 18, removed: 6, total 12
@@ -438,6 +438,7 @@ Pipeline Mos6502::parse_next_instruction() {
case Instruction::NopImpliedDA:
case Instruction::NopImpliedFA:
case Instruction::NopImmediate80:
case Instruction::NopImmediate82:
case Instruction::NopZeropage04:
case Instruction::NopZeropageX14:
case Instruction::NopZeropageX34:
 
core/test/src/opcode.h added: 18, removed: 6, total 12
@@ -123,6 +123,7 @@ enum Opcode : uint8_t {
RRA_ABSX = 0x7F,
NOP_IMM80 = 0x80,
STA_INXIND = 0x81,
NOP_IMM82 = 0x82,
SAX_INXIND = 0x83,
STY_ZERO = 0x84,
STA_ZERO = 0x85,
 
core/test/src/test_cpu.cpp added: 18, removed: 6, total 12
@@ -566,6 +566,13 @@ TEST_F(CpuTest, nop80_immediated) {
step_execution(2);
EXPECT_EQ(expected, registers);
}
TEST_F(CpuTest, nop82_immediated) {
stage_instruction(NOP_IMM82);
expected.pc += 1;
 
step_execution(2);
EXPECT_EQ(expected, registers);
}
TEST_F(CpuTest, nop04_zero) {
stage_instruction(NOP_ZERO04);
expected.pc += 1;
 
romtest/test_rom.py added: 18, removed: 6, total 12
@@ -104,7 +104,7 @@ TESTS = [
pass_pattern="Passed",
cycles=100000000,
failing=True,
), # Missing opcode 0x82
), # Missing opcode 0x89
Test(
rom="instr_test-v5/rom_singles/04-zero_page.nes",
pass_pattern="Passed",