srctree

Johan parent 91a197ec f1221d95 16e626fd
Merge pull request #367 from johnor/default-compare-operator-ppu

Default compare operator ppu
core/include/nes/core/ppu_registers.h added: 85, removed: 19, total 66
@@ -181,6 +181,9 @@ struct PpuRegisters {
uint8_t attribute_table_latch;
uint16_t attribute_table_shifter_low;
uint16_t attribute_table_shifter_hi;
 
[[nodiscard]] constexpr bool operator==(
const PpuRegisters &) const = default;
};
 
} // namespace n_e_s::core
 
core/src/ppu.cpp added: 85, removed: 19, total 66
@@ -215,7 +215,6 @@ void Ppu::increment_vram_address() {
 
void Ppu::execute_pre_render_scanline() {
fetch();
shift_registers();
increase_scroll_counters();
if (cycle() == 1) {
clear_vblank_flag();
@@ -224,7 +223,6 @@ void Ppu::execute_pre_render_scanline() {
 
void Ppu::execute_visible_scanline() {
fetch();
shift_registers();
increase_scroll_counters();
}
 
@@ -296,6 +294,7 @@ void Ppu::increase_scroll_counters() {
void Ppu::fetch() {
if ((cycle() >= 1 && cycle() <= 256) ||
(cycle() >= 321 && cycle() <= 336)) {
shift_registers();
const uint16_t background_pattern_table_base_address =
(registers_->ctrl & 0b0001'0000u) ? 0x1000u : 0x0000u;
const uint8_t fine_scroll_y = registers_->vram_addr.fine_scroll_y();
 
core/test/src/ippu_helpers.cpp added: 85, removed: 19, total 66
@@ -5,14 +5,6 @@
 
namespace n_e_s::core {
 
bool operator==(const PpuRegisters &a, const PpuRegisters &b) {
return a.scanline == b.scanline && a.cycle == b.cycle && a.ctrl == b.ctrl &&
a.mask == b.mask && a.status == b.status && a.oamaddr == b.oamaddr &&
a.fine_x_scroll == b.fine_x_scroll && a.vram_addr == b.vram_addr &&
a.temp_vram_addr == b.temp_vram_addr &&
a.write_toggle == b.write_toggle && a.odd_frame == b.odd_frame;
}
 
// Required by gtest to use pascal case.
// NOLINTNEXTLINE(readability-identifier-naming)
void PrintTo(const PpuRegisters &r, std::ostream *os) {
@@ -20,7 +12,10 @@ void PrintTo(const PpuRegisters &r, std::ostream *os) {
"Cycle: {} Scanline: {} Ctrl: {:#04x} ScrollX: {:#04x} Mask: "
"{:#04x} OamAddr: {:#04x} "
"Status: {:#04x} VramAddr: {:#06x} TmpVramAddr: {:#06x} "
"WriteToggle: {} OddFrame: {}\n",
"WriteToggle: {} OddFrame: {} NameTbl: {:#04x}[{:#04x}] "
"PatternTblHi: {:#06x}[{:#04x}] "
"PatternTblLow: {:#06x}[{:#04x}] "
"Attr: {:#06x}:{:#06x}[{:#04x}]\n",
r.cycle,
r.scanline,
r.ctrl,
@@ -31,7 +26,16 @@ void PrintTo(const PpuRegisters &r, std::ostream *os) {
r.vram_addr.value(),
r.temp_vram_addr.value(),
r.write_toggle,
r.odd_frame);
r.odd_frame,
r.name_table,
r.name_table_latch,
r.pattern_table_shifter_hi,
r.pattern_table_latch_hi,
r.pattern_table_shifter_low,
r.pattern_table_latch_low,
r.attribute_table_shifter_low,
r.attribute_table_shifter_hi,
r.attribute_table_latch);
}
 
} // namespace n_e_s::core
 
core/test/src/ippu_helpers.h added: 85, removed: 19, total 66
@@ -6,8 +6,6 @@
 
namespace n_e_s::core {
 
bool operator==(const PpuRegisters &a, const PpuRegisters &b);
 
// Required by gtest to use pascal case.
// NOLINTNEXTLINE(readability-identifier-naming)
void PrintTo(const PpuRegisters &r, std::ostream *os);
 
core/test/src/test_ppu.cpp added: 85, removed: 19, total 66
@@ -466,6 +466,15 @@ TEST_F(PpuTest, visible_two_sub_cycles) {
expected.cycle = 17;
// Vram should be increased at cycle 8 and 16
expected.vram_addr = PpuVram(0x0002);
expected.name_table = 0x02;
expected.name_table_latch = 0x03;
expected.pattern_table_shifter_hi = 0x4C80;
expected.pattern_table_latch_hi = 0x99;
expected.pattern_table_shifter_low = 0x4000;
expected.pattern_table_latch_low = 0x80;
expected.attribute_table_shifter_low = 0x7F80;
expected.attribute_table_shifter_hi = 0x7F80;
expected.attribute_table_latch = 0x03;
 
// Clear scrolling
ppu->write_byte(0x2005, 0);
@@ -519,6 +528,15 @@ TEST_F(PpuTest, visible_scanline) {
// Fine scroll should be increase once, and coarse x for each tile except
// the last (31x).
expected.vram_addr = PpuVram(0b001'00'00000'11111);
expected.name_table = 0x1E;
expected.name_table_latch = 0x1F;
expected.pattern_table_shifter_hi = 0x8700;
expected.pattern_table_latch_hi = 0x0F;
expected.pattern_table_shifter_low = 0x8F00;
expected.pattern_table_latch_low = 0x1F;
expected.attribute_table_shifter_low = 0xFF80;
expected.attribute_table_shifter_hi = 0x8000;
expected.attribute_table_latch = 0x01;
 
// Clear scrolling
ppu->write_byte(0x2005, 0);
@@ -559,6 +577,7 @@ TEST_F(PpuTest, visible_scanline) {
// Cycle 258-320
// During cycle 280-304 the ppu is idle
expected.cycle = 321;
 
for (int i = 258; i <= 320; ++i) {
const auto pixel = ppu->execute();
EXPECT_FALSE(pixel.has_value());
@@ -569,6 +588,16 @@ TEST_F(PpuTest, visible_scanline) {
// Fetch first two tiles for next scanline (fine scroll y=1)
expected.vram_addr = PpuVram(0b001'00'00000'00010);
expected.cycle = 337;
expected.name_table = 0x02;
expected.name_table_latch = 0x03;
expected.pattern_table_shifter_hi = 0xCC80;
expected.pattern_table_latch_hi = 0x99;
expected.pattern_table_shifter_low = 0xC000;
expected.pattern_table_latch_low = 0x80;
expected.attribute_table_shifter_low = 0xFF80;
expected.attribute_table_shifter_hi = 0x7F80;
expected.attribute_table_latch = 0x03;
 
// Nametables
EXPECT_CALL(mmu, read_byte(0x2000)).WillOnce(Return(0x02));
EXPECT_CALL(mmu, read_byte(0x2001)).WillOnce(Return(0x03));
@@ -592,6 +621,8 @@ TEST_F(PpuTest, visible_scanline) {
// Two unused nametable fetches.
expected.scanline = 1;
expected.cycle = 0;
expected.name_table = 0x02;
expected.name_table_latch = 0x02;
EXPECT_CALL(mmu, read_byte(0x2000 + 2)).Times(2).WillRepeatedly(Return(2));
for (int i = 337; i <= 340; ++i) {
const auto pixel = ppu->execute();
@@ -608,6 +639,15 @@ TEST_F(PpuTest, pre_render_two_sub_cycles) {
expected.cycle = 17;
// Vram should be increased at cycle 8 and 16
expected.vram_addr = PpuVram(0x0002);
expected.name_table = 0x02;
expected.name_table_latch = 0x03;
expected.pattern_table_shifter_hi = 0x4C80;
expected.pattern_table_latch_hi = 0x99;
expected.pattern_table_shifter_low = 0x4000;
expected.pattern_table_latch_low = 0x80;
expected.attribute_table_shifter_low = 0x7F80;
expected.attribute_table_shifter_hi = 0x7F80;
expected.attribute_table_latch = 0x03;
 
// Clear scrolling
ppu->write_byte(0x2005, 0);
@@ -664,6 +704,15 @@ TEST_F(PpuTest, pre_render_scanline) {
// Fine scroll should be increase once, and coarse x for each tile except
// the last (31x).
expected.vram_addr = PpuVram(0b001'00'00000'11111);
expected.name_table = 0x1E;
expected.name_table_latch = 0x1F;
expected.pattern_table_shifter_hi = 0x8700;
expected.pattern_table_latch_hi = 0x0F;
expected.pattern_table_shifter_low = 0x8F00;
expected.pattern_table_latch_low = 0x1F;
expected.attribute_table_shifter_low = 0xFF80;
expected.attribute_table_shifter_hi = 0x8000;
expected.attribute_table_latch = 0x01;
 
// Clear scrolling
ppu->write_byte(0x2005, 0);
@@ -705,6 +754,7 @@ TEST_F(PpuTest, pre_render_scanline) {
// During cycle 280-304 the vertical scroll bits should be reloaded.
expected.vram_addr = PpuVram(0b000'00'00000'00000);
expected.cycle = 321;
 
for (int i = 258; i <= 320; ++i) {
const auto pixel = ppu->execute();
EXPECT_FALSE(pixel.has_value());
@@ -715,6 +765,16 @@ TEST_F(PpuTest, pre_render_scanline) {
// Fetch first two tiles for next scanline.
expected.vram_addr = PpuVram(0b000'00'00000'00010);
expected.cycle = 337;
expected.name_table = 0x02;
expected.name_table_latch = 0x03;
expected.pattern_table_shifter_hi = 0xCC80;
expected.pattern_table_latch_hi = 0x99;
expected.pattern_table_shifter_low = 0xC000;
expected.pattern_table_latch_low = 0x80;
expected.attribute_table_shifter_low = 0xFF80;
expected.attribute_table_shifter_hi = 0x7F80;
expected.attribute_table_latch = 0x03;
 
// Nametables
EXPECT_CALL(mmu, read_byte(0x2000)).WillOnce(Return(0x02));
EXPECT_CALL(mmu, read_byte(0x2001)).WillOnce(Return(0x03));
@@ -739,6 +799,8 @@ TEST_F(PpuTest, pre_render_scanline) {
expected.scanline = 0;
expected.cycle = 0;
expected.odd_frame = false;
expected.name_table = 0x02;
expected.name_table_latch = 0x02;
EXPECT_CALL(mmu, read_byte(0x2000 + 2)).Times(2).WillRepeatedly(Return(2));
for (int i = 337; i <= 340; ++i) {
const auto pixel = ppu->execute();